1. Field of the Invention
The present invention relates generally to a frequency shifter used for wireless communication systems and more particularly relates to an arbitrary frequency shifter extremely useful for a digital communication system designed to operate with various communication systems which are centered at different frequencies in the frequency domain.
2. Background Art
Various wireless standards and communication systems are available in the market, e.g., cellular phones, wireless local area network (WLAN) systems, and Bluetooth devices. In practice, the signal is up-converted to a much higher radio frequency (RF) and is transmitted. It is the designer's choice to down-convert the RF signal directly to baseband or through an intermediate frequency (IF) first and then apply a digital phase shifter to down-convert the signal to baseband. With the growth of markets, it is of great interests to integrate different systems into a single device. One solution is to have one set of front-end analog or digital device for each communication system. The other better solution is to design only one front-end analog or digital device capable of operating at different RF or IF frequencies of different communication systems. The present invention theoretically provides the general theory to design a common digital phase shifter capable of performing arbitrary frequency shifts.
FIG. 1 shows the general implementations of a frequency shifter of the prior art. The conventional frequency shifter 100 mainly comprises a positive or negative frequency shift controller 110, a phase accumulator 120, a sine and cosine function calculator 130 and a phase shifter 140. A general frequency shifter 100 is used to shift an arbitrary frequency of the original signal in the frequency domain. The positive or negative frequency shift controller 110 is used to provide the 1-bit controller PN which controls sign indicators S2 and S1. The phase accumulator 120, receiving a phase increment per sampling instant, φ, and the sign indicator S1, is used to output a phase accumulation θn to the sine and cosine function calculator 130. The sine and cosine function calculator 130, receiving the phase accumulation, θn, is used to provide sine and cosine values to the phase shifter 140. The phase shifter 140, receiving the sine and cosine values from the sine and cosine function calculator 130 and the sign indicators S2, is used to output a complex signal, Ĩn+j{tilde over (Q)}n, with a frequency shift equal to ±fΔ of the input signal, In+jQn.
The procedure is described as follows:
                                                        I              ~                        n                    +                      j            ⁢                                          Q                ~                            n                                      =                                            (                                                I                  n                                +                                  jQ                  n                                            )                        ⁢                          ⅇ                                                ±                                      j2π                    ⁡                                          (                                                                        f                          Δ                                                                          f                          s                                                                    )                                                                      ⁢                n                                              ≡                                    (                                                I                  n                                +                                  jQ                  n                                            )                        ⁢                          ⅇ                                                j                  ⁡                                      (                                          1                      -                                              2                        ×                        PN                                                              )                                                  ⁢                n                ⁢                                                                  ⁢                ϕ                                              ≡                                    (                                                I                  n                                +                                  jQ                  n                                            )                        ⁢                          ⅇ                                                j                  ⁡                                      (                                                                  S                        1                                            ⁢                                              S                        2                                                              )                                                  ⁢                n                ⁢                                                                  ⁢                ϕ                                                                        (                  EQ          ⁢                      -                    ⁢          1                )            where
  ϕ  ≡      2    ⁢          π      ⁡              (                              f            Δ                                f            s                          )            is the phase increment per sampling instant and the input to the phase accumulator 120, In+jQn is the input signal of the phase shifter 140, n is the discrete time index in the digital implementation, ±fΔ is the desired positive or negative frequency shift, fs is the sampling frequency, and the output signal of the phase shifter 140, Ĩn+j{tilde over (Q)}n, is a complex signal with a frequency shift equal to ±fΔ of the input signal. Without loss of generality, fΔ, fs and φ are assumed to be positive real numbers and the discrete time index, n, is assumed to be either zero or an arbitrary positive integer. To be more specific:(a) For a positive frequency shift (when PN=0, 1-2×PN=S1S2=1):Ĩn+j{tilde over (Q)}n≡(In+jQn)e+jnφ  (EQ-2a)(a) For a negative frequency shift (when PN=1, 1-2×PN=S1S2=−1):Ĩn+j{tilde over (Q)}n≡(In+jQn)e−jnφ.  (EQ-2b)
Two implementations of (EQ-2a) for a positive frequency shift are described in the following equations:Ĩn=In cos(nφ)−Qn sin(nφ) and {tilde over (Q)}n=Qn cos(nφ)+In sin(nφ)  (EQ-3a)Ĩn=In cos(−nφ)+Qn sin(−nφ) and {tilde over (Q)}n=Qn cos(−nφ)+In sin(−nφ)  (EQ-3b)
On the other hand, the implementations of (EQ-2b) for a negative frequency shift are derived as follows:Ĩn=In cos(nφ)+Qn sin(nφ) and {tilde over (Q)}n=Qn cos(nφ)−In sin(nφ)  (EQ-4a)Ĩn=In cos(−nφ)−Qn sin(−nφ) and {tilde over (Q)}n=Qn cos(−nφ)+In sin(−nφ)  (EQ-4b)After applying the arithmetic properties of sine and cosine functions in (Eq-1):cos(S2S1×nφ)=cos(S1×nφ), sin(S2S1×nφ)=S2 sin(S1×nφ),a general structure which includes both (EQ-3) and (EQ-4) is described as followsĨn=In cos(S1×nφ)−S2×Qn sin(S1×nφ){tilde over (Q)}n=Qn cos(S1×nφ)+S2×In sin(S1×nφ)  (EQ-5)where the sign indicators, S1 and S2, provided by the positive or negative frequency shift controller 110, is either 1 or −1. The relationship of the resulting frequency shift and the sign indicators is shown in the Table 1. According to (Eq-1), the one-bit controller determines either a positive (+fΔ>0) or a negative frequency shift (−fΔ<0) is performed. According to (Eq-3), the phase accumulation (θn) of a positive frequency shift can be implemented from adding up a positive or a negative phase increment φ, i.e., +nφ or −nφ. On the other hand, the phase accumulation (θn) of a negative frequency shift can also be implemented from adding up a positive or a negative phase increment φ, i.e., +nφ or −nφ, from (Eq-4). In short, (Eq-5) can perform either a positive or a negative frequency shift if the following relation holds:1-2×PN=S1S2, PN=0,1, S1, S2=1,−1.
Therefore, any sub-equation in (EQ-3) can be implemented as a positive frequency shifter and any sub-equation in (EQ-4) can be implemented as a negative frequency shifter. Furthermore, any sub-equation in (EQ-3) together with any sub-equation in (EQ-4) can be implemented as a frequency shifter which is capable of both positive and negative frequency shift of a signal. However, any above implementation requires a tracking of the phase accumulation, i.e., ±nφ, which is output from the phase accumulator 120, can be easily implemented without the multiplication of the time index n as follows
                              θ          n                =                                            ±                              n                ⁡                                  (                                                            2                      ⁢                      π                      ⁢                                                                                          ⁢                                              f                        Δ                                                                                    f                      s                                                        )                                                      ≡                                          ±                n                            ⁢                                                          ⁢              ϕ                                =                                                    θ                                  n                  -                  1                                            ±                              ϕ                ⁢                                                                  ⁢                where                ⁢                                                                  ⁢                ϕ                                      ≡                                                            2                  ⁢                  π                  ⁢                                                                          ⁢                                      f                    Δ                                                                    f                  s                                            .                                                          (                  EQ          ⁢                      -                    ⁢          6                )            
A few practical digital implementation notes are discussed in the following:
1) Since sin(2πN+θ)=sin θ and cos(2πN+θ)=cos θ for an arbitrary integer N, only the result after modulo 2π operation of θn, or that after the modulo 2π operation of nφ or −nφ, is required to be implemented.
2) (EQ-6) avoids the multiplication of an arbitrary integer n. However, only finite bits are allowed in the digital implementation to represent the phase increment, φ. In other words,
                              ϕ          ≡                                                    (                                                      2                    ⁢                    π                    ⁢                                                                                  ⁢                                          f                      Δ                                                                            f                    s                                                  )                                            finite                -                bits                                      +                          Δϕ              q                                      =                              2            ⁢                          π              ⁡                              (                                                                            f                      Δ                                        +                                                                  f                        s                                            ⁢                                                                        Δϕ                          q                                                /                        2                                            ⁢                      π                                                                            f                    s                                                  )                                              ≡                                    2              ⁢              π              ⁢                                                          ⁢                              (                                                      f                    Δ                                    +                                                            f                      ^                                        Δ                                                  )                                                    f              s                                                          (                  EQ          ⁢                      -                    ⁢          7                )            where Δφq is the quantization error due to the finite-bit representation. This quantization error will introduce an undesired frequency error which results an accumulated phase error fs times added after each sampling instant if it is not tracked and compensated. The required bits are proportional to the required frequency accuracy and the length of the signal, i.e., the discrete time index, n. For example, if the quantization error is required to be around one part-per-million (PPM) of the normalized sampling frequency, i.e., Δφq<10−6, then it will require about log2 (106) or 20 bits to represent just the value of φ below the decimal point. Therefore, it requires about 23 bits to represent the phase increment, φ, from 0 to 2π and a 23-bit addition to obtain the phase accumulation, θn, in (EQ-6).3) To calculate each pair of output from (EQ-3) and (EQ-4), a pair of sine and cosine values, cos θ and sin θ shall be provided by the sine and cosine function calculator 130. For a high-speed implementation, i.e., fs>>1 Hz, it is convenient to apply the Look-Up-Tables (LUTs) to obtain both sine and cosine values without extra calculations at every sampling instant.
In this case, only a finite number of entries of the LUTs are allowed to be implemented in a practical digital system. Therefore, the phase accumulation, θn, will be further quantized to one of the available entries of the LUTs. Several, but not limited, implementations from A.1 to A.4 which are capable of both positive and negative frequency shift are illustrated in FIG. 1. The corresponding controls are listed in Table 2. According to Implementation A.1, the phase accumulation is tracked from a positive phase, +nφ, only. On the other hand, the phase accumulation is tracked from a negative phase, −nφ, only in the implementation A.2. Finally, the implementations A.3 and A.4 track a phase which is either positive or negative, i.e., ±nφ. These three tracking methods are the basic implementations of this invention.